Functional Verification of Programmable Embedded Architectures: A Top-Down Approach by Nikil D. Dutt
Springer; 2005 edition | August 1, 2005 | English | ISBN: 0387261435 | 186 pages | PDF | 9 MB
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation.